1. Field of the Invention
The present invention relates to a protecting circuit of a transistor.
2. Description of the Related Art
In recent years, a gate length is reduced with the improvement of process technique, so that the switching speed of a power MOS transistor is increased. As a result, the rising edge and falling edge of output current of the power MOS transistor become steep. Therefore, in the power MOS transistor, various problems, such as the change of a power supply voltage and the radiation of noise, are caused by the steep change of the output current.
Generally, as shown in FIGS. 1 and 2, the gates of power MOS transistors 1 and 2 are driven with gate signals from inverters (buffers) 8 and 9, respectively. Therefore, conventionally, the sizes of output transistors in the buffers 8 and 9 are adjusted such that output resistances are made large. Instead, high resistances 18 and 19 are inserted between the buffers 8 and 9 and the gates of the power MOS transistors 1 and 2 to make the gate signals less steep by the resistances 18 and 19 and capacitances 16 and 17 between and the gates and drains of the power MOS transistors 1 and 2. As a result, a rising time and a falling time are made long in the output current waveforms of the power MOS transistors 1 and 2.
However, in a first conventional example, the ability to drive the gate of the power MOS transistor is reduced. When the voltage of a load connection terminal changes by a large amount, charging and discharging currents flow through the capacitance 16 or 17 between the gate and the drain. In this case, the voltage levels a1xe2x80x2 and a2xe2x80x2, and b1xe2x80x2 and b2xe2x80x2 of the gate signals ga and gb is changed, as shown in FIG. 8. As a result, the power MOS transistor 1 or the power MOS transistor 2 is erroneously turned on, so that the current flows between the power supply and the ground. When the gate voltages exceed the breakdown voltages of the power MOS transistors 1 and 2, the power MOS transistors 1 and 2 are possibly destroyed.
In conjunction with the above description, an H bridge protecting circuit is known in Japanese Laid Open Patent Application (JP-A-Heisei 1-91620). In this reference, an H bridge circuit is composed of a direct current power supply and four semiconductor devices. A control circuit controls each of the four semiconductor devices to be in a conductive or non-conductive state such that a motor is rotated in a positive direction or in an reverse direction. A stopping circuit detects an over-voltage or a surge voltage generated in the direct current power supply and controls all the four semiconductor devices to set to the non-conductive state. An over-current detecting circuit detects an over-current flowing through any of the four semiconductor devices. When the over-current detecting circuit detects the over-current, the stopping circuit controls all the four semiconductor devices to set to the non-conductive state.
Also, a semiconductor circuit apparatus is known in Japanese Laid Open Patent Application (JP-A-Heisei 2-58372). In this reference, a vertical type insulating gate field effect element is used as a pull-up element, in which a semiconductor substrate is used as a drain or an anode terminal. Also, an insulating gate field effect element is used as a pull-down element, which is formed in an N-type region separated by a P-type region.
Also, a through current preventing circuit is known in Japanese Laid Open Patent Application (JP-A-Heisei 4-331492). In this reference, an H bridge circuit is composed of two P-channel MOS transistors (9, 10) and two N-channel MOS transistors (11, 12). A through current preventing circuit is composed of first and second buffer circuits (16) in which a rising time of an output signal is longer than a falling time of the output signal, third and fourth buffer circuits (18) in which a falling time of an output signal is longer than a rising time of the output signal, and fifth and eighth buffer circuits, (17, 19) in which a rising time of an output signal is equal to a falling time of the output signal. As a result, there is no operation period of all the MOS transistors (9 to 12). Thus, the through current can be prevented. A high frequency operation of the H bridge circuit is made possible if the duty ratios of drive signals (1 and 2) are determined in consideration of a non-operation period.
Also, an electrostatic discharge(ESD) protecting circuit is known in Japanese Laid Open Patent Application (JP-A-Heisei 8-55958 corresponding to U.S. patent application No. 08/280417). In this reference, the ESD protecting circuit is composed of a first n+-type diode whose cathode is connected to a pad and whose anode is connected to a substrate ground. The first diode is composed of a substrate of one of a Pxe2x88x92-type and a Pxe2x88x92 on P+-type epitaxial type, and an N+-type region deposited on the substrate. Also, the first diode is further composed of a P+-type region deposited on the substrate and connected to the substrate ground, and a field oxidation film region formed to electrically insulate the N+-type region from the P+-type region. Also, the first diode is further composed of an N-type well surrounding the N+-type region to prevent avalanche from being generated in the first diode in response to an input voltage applied to the pad and lower than a predetermined voltage.
Also, a voice coil motor feedback control circuit is known in Japanese Laid Open Patent Application (JP-A-Heisei 8-163885 corresponding to U.S. patent application Ser. No. 08/300952). In this reference, the voice coil motor feedback control circuit is composed of an H bridge circuit (10), a controller (20) and a feed back loop (60). The feed back loop (60) prevents the voltage applied to the voice coil motor from increasing due to counter-electromotive force.
Therefore, an object of the present invention is to provide a transistor protecting circuit.
Another object of the present invention is to provide a transistor protecting circuit which can prevents an erroneous operation of a transistor and the destruction of the transistor.
Still another object of the present invention is to provides a transistor protecting circuit which can prevent through current from flowing between a power supply and the ground.
Yet still another object of the present invention is to provide a transistor protecting circuit in which the current drive ability to a gate of a transistor is enhanced.
It is another object of the present invention is to provide a transistor protecting circuit which is provided with an inverter, an RS latch, and an enhancing transistor.
In order to achieve an aspect of the present invention, a transistor protecting circuit for an H bridge circuit includes first to fourth buffers, and an enhancing circuit. The H bridge circuit includes a first P-channel transistor and a first N-channel transistor provided between a first power supply and a ground to be connected in series through a first node, and a second P-channel transistor and a second N-channel transistor provided between the first power supply and the ground to be connected in series through a second node. A load is connected between the first node and the second node. The first buffer inverts a first control signal to a first gate signal which is supplied to a gate of the first P-channel transistor via a first line, and the second buffer inverts a second control signal to a second gate signal which is supplied to a gate of the first N-channel transistor via a second line. Also, the third buffer inverts a third control signal a third gate signal which is supplied to a gate of the second P-channel transistor via a third line, and the fourth buffer inverts a fourth control signal to a fourth gate signal which is supplied supply to a gate of the second N-channel transistor via a fourth line. The third and fourth control signals are inverted to the first and second gate signals. The enhancing circuit selectively passes current into or from one of the first to fourth lines based on the first to the fourth control signals.
Here, the enhancing circuit passes first current onto the first line when the first N-channel transistor is turned on in response to the second gate signal while the first P-channel transistor is in an off state in response to the first gate signal, and supplies second current from the second line when the first P-channel transistor is turned on in response to the first gate signal while the first N-channel transistor is in an off state in response to the second gate signal. Also, the enhancing circuit passes third current onto the third line when the second N-channel transistor is turned on in response to the fourth gate signal while the second P-channel transistor is in an off state in response to the third gate signal, and passes fourth current from the fourth line when the second P-channel transistor is turned on in response to the third gate signal while the second N-channel transistor is in an off state in response to the fourth gate signal.
Also, the enhancing circuit may include a first enhancing circuit and a second enhancing circuit. The first enhancing circuit is provided for the first P-channel transistor and the first N-channel transistor to selectively current into the first line and from the second line based on the first and second gate signals. Also, the second enhancing circuit is provided for the second P-channel transistor and the second N-channel transistor to selectively passes current into the third line and from the fourth line based on the third and fourth gate signals. In this case, the first enhancing circuit passes first current onto the first line when the first N-channel transistor is turned on in response to the second gate signal while the first P-channel transistor is in an off state in response to the first gate signal, and passes second current from the second line when the first P-channel transistor is turned on in response to the first gate signal while the first N-channel transistor is in an off state in response to the second gate signal. Also, the second enhancing circuit passes third current onto the third line when the second N-channel transistor is turned on in response to the fourth gate signal while the second P-channel transistor is in an off state in response to the third gate signal, and passes fourth current from the fourth line when the second P-channel transistor is turned on in response to the third gate signal while the second N-channel transistor is in an off state in response to the fourth gate signal. Also, the first enhancing circuit may include a first P-channel control transistor, a first N-channel control transistor and a first timing circuit. The second enhancing circuit may include a second P-channel control transistor, a second N-channel control transistor and a second timing circuit. The first P-channel control transistor is provided between a second power supply and the first line, and passes first current from the second power supply to the first line in response to a first drive signal. The first N-channel control transistor is provided between the ground and the second line, and passes second current from the second line to the ground in response to the first drive signal. The first timing circuit generates the first drive signal based on the first and second control signals. The second P-channel control transistor is provided between the second power supply and the third line, and passes third current from the second power supply to the third line in response to a second drive signal. The second N-channel control transistor is provided between the ground and the fourth line, and passes fourth current from the fourth line to the ground in response to the second drive signal. The second timing circuit generates the second drive signal based on the third and fourth control signals. In this case, the first timing circuit may include a first flip-flop circuit set in response to a rising edge of the first control signal and reset in response to a falling edge of an inversion signal of the second control signal. Also, the second timing circuit may include a second flip-flop circuit set in response to a rising edge of the third control signal and reset in response to a falling edge of an inversion signal of the fourth control signal.
Also, an internal resistor of the first buffer is larger than a sum of an internal resistor of the first P-channel control transistor and a resistive element provided between the first P-channel control transistor and the first line. An internal resistor of the second buffer is larger than a sum of an internal resistor of the first N-channel control transistor and a resistive element provided between the first N-channel control transistor and the second line. An internal resistor of the third buffer is larger than a sum of an internal resistor of the second P-channel control transistor and a resistive element provided between the second P-channel control transistor and the third line. An internal resistor of the fourth buffer is larger than a sum of an internal resistor of the second N-channel control transistor and a resistive element provided between the second N-channel control transistor and the fourth line.
In order to achieve another aspect of the present invention, a method of protecting an H bridge circuit is provided. In the H bridge circuit, a first P-channel transistor and a first N-channel transistor are provided between a first power supply and a ground to be connected in series through a first node, and a second P-channel transistor and a second N-channel transistor are provided between the first power supply and the ground to be connected in series through a second node. A load is connected between the first node and the second node. The first to fourth transistors having first to fourth capacitances each of which is a capacitance between a gate and a drain, respectively. The method includes: driving the first to fourth transistors through first to fourth lines in response to first to fourth control signals, respectively; and selectively charging the first to fourth third capacitances based on the first to the fourth control signals.
In this case, the charging operation includes: charging the first capacitance in response to turning on of the first N-channel transistor while the first P-channel transistor is in an off state; and charging the third capacitance in response to turning on of the second N-channel transistor while the second P-channel transistor is in an off state. Also, the charging operation includes: charging the second capacitance in response to turning on of the first P-channel transistor while the first N-channel transistor is in an off state; and charging the fourth capacitance in response to turning on of the second P-channel transistor while the second N-channel transistor is in an off state.
Also, when the method may further include generating first and second drive signals from the first to fourth control signals. At this time, the selectively charging operation includes: charging the first capacitance in response to the first drive signal; and charging the third capacitance in response to the second drive signal. Also, the selectively charging operation includes: charging the second capacitance in response to the first drive signal; and charging the fourth capacitance in response to the second drive signal. In this case, the generating operation includes: generating the first drive signal to have a high level in response to a rising edge of the first control signal and a low level in response to a falling edge of an inversion signal of the second control signal; and generating the second drive signal to have a high level in response to a rising edge of the third control signal and a low level in response to a falling edge of an inversion signal of the fourth control signal.
In order to achieve still another aspect of the present invention, a transistor protecting circuit for an H bridge circuit includes a driving section and an enhancing section. In the H bridge circuit, a first P-channel transistor and a first N-channel transistor are provided between a first power supply and a ground to be connected in series through a first node, and a second P-channel transistor and a second N-channel transistor are provided between the first power supply and the ground to be connected in series through a second node. A load is connected between the first node and the second node. The first to fourth transistors have first to fourth capacitances each of which is a capacitance between a gate and a drain, respectively. The driving section drives the first to fourth transistors through first to fourth lines in response to first to fourth control signals, respectively. The enhancing section selectively charges the first to fourth capacitances based on the first to the fourth control signals.
Here, the enhancing section may include a first charging section charging the first capacitance in response to turning on of the first N-channel transistor while the first P-channel transistor is in an off state; a second charging section for charging the third capacitance in response to turning on of the second N-channel transistor while the second P-channel transistor is in an off state; a third charging section charging the second capacitance in response to turning on of the first P-channel transistor while the first N-channel transistor is in an off state; and a fourth charging section for charging the fourth capacitance in response to turning on of the second P-channel transistor while the second N-channel transistor is in an off state.
Also, the enhancing section may include a generating section generating first and second drive signals from the first to fourth control signals, a first charging section charging the first capacitance in response to the first drive signal; a second charging section charging the third capacitance in response to the second drive signal; a third charging section charging the second capacitance in response to the first drive signal; and a fourth charging section charging the fourth capacitance in response to the second drive signal.
Also, the generating section may include a first generating section generating the first drive signal to have a high level in response to a rising edge of the first control signal and a low level in response to a falling edge of an inversion signal of the second control signal; and a second generating section generating the second drive signal to have a high level in response to a rising edge of the third control signal and a low level in response to a falling edge of an inversion signal of the fourth control signal.
Also, the first charging section includes a first P-channel control transistor, the first discharging section includes a first N-channel control transistor, the second charging section includes a second P-channel control transistor, and the second discharging section includes a second N-channel control transistor. In this case, a sum of an internal resistor of the first buffer and a resistive element provided between the first buffer and the first transistor gate is larger than a sum of an internal resistor of the first P-channel control transistor and a resistive element provided between the first P-channel control transistor and the first transistor gate. Also, a sum of an internal resistor of the second buffer and a resistive element provided between the second buffer and the second transistor gate is larger than a sum of an internal resistor of the first N-channel control transistor and a resistive element provided between the first N-channel control transistor and the second transistor gate. Also, a sum of an internal resistor of the third buffer and a resistive element provided between the third buffer and the third transistor gate is larger than a sum of an internal resistor of the second P-channel control transistor and a resistive element provided between the second P-channel control transistor and the third transistor gate. Also, a sum of an internal resistor of the fourth buffer and a resistive element provided between the fourth buffer and the fourth transistor gate is larger than a sum of an internal resistor of the second N-channel control transistor and a resistive element provided between the second N-channel control transistor and the fourth transistor gate.